The inventive concepts described herein generally relate to methods for fabricating semiconductor devices.
In order to meet superior performance and low cost that users desire, there has been a demand for increasing integration density of semiconductor devices. In the case of a semiconductor memory device, its integration density is a main factor for deciding the prices of products, and thus, a demand for higher integration density has increased. In the case of a conventional two-dimensional or planar semiconductor memory device, its integration density is mainly decided by the area that a unit memory cell occupies, and thus, its integration density is significantly affected by the level of technique for forming fine patterns. However, since ultra high-cost equipment is needed for fine patterns, the integration density of the two-dimensional semiconductor memory device is increasing but remains relatively expensive and/or restrictive.
In recent years, three-dimensional semiconductor memory devices, including three-dimensionally arranged memory cells, have been proposed to overcome the above limitations. However, for mass production of three-dimensional semiconductor memory devices, there has been a need for process technology that is capable of reducing manufacturing cost per bit of a three-dimensional semiconductor memory device more than that of a two-dimensional semiconductor memory device and/or implementing reliable product characteristics.